A sequential regulation system, a combination of units regulated following sequential commands, such as a counter, a register, a memory, a ratch, a flip-flop circuit et al. each of which works following a clock pulse or clock pulses, requires a clock circuit generating and supplying a series of clock pulses having a regular time interval therebetween. Particularly in a synchronous system, uniformity of clock pulses is important. In other words, each end terminal is required to be given clock pulses simultaneously or precisely on the same time.
Since the circuit constant particularly the resistance of each of the clock pulse transmission circuits is not necessarily uniform, however, it is not easy to make the clock pulse transmission period uniform for all the clock pulse transmission circuits, particularly in the cases where the sequential regulation system is large, and resultantly the sequential regulation system having a number of the destination units each of which requires to the given a clock signal. This problem is more severe for a sequential regulation system having multiple functions. As a result, in such a case as was described above, each clock pulse does not necessarily arrive at each destination unit at the same time. This phenomenon in which each clock pulse arrives at each destination unit with a time difference, is called a clock skew. Developed to avoid occurrence of a clock skew is a clock circuit having a construction of multiple stories in which a clock circuit is composed of a plurality of stories each of which is composed of a combination of a trunk line and plural branch lines, as shown in FIG. 1. Referring to FIG. 1, the first story is composed of a trunk line (1) and 10 branch lines (2), and the second story is composed of a plurality of combinations of a trunk line (1') and five branch lines (2'). Since all the functional units which require a clock pulse simultaneously can be designed to follow the same story, occurrence of a clock skew can be avoided.
A clock pulse circuit having a construction of multiple stories available in the prior art is designed, however, to give clock pulses to all the units which require such clock pulses, regardless some of the units really require the clock pulses during a specific period or regardless some of the units belong to a specific family or a group of units required for accomplishment of a specific function.
It is needless to emphasize that supply of clock pluses requires power consumption more or less. Insofar as a small sized clock pulse circuit is concerned, the amount of such power consumption as is employed by a system in which clock pulses are given to all the destination units, regardless of real requirement, is marginal. When it comes to large scale clock pulse circuit, it is a different story.